SAVE THE DATE Tapia 2018 Orlando, FL September 19-22, 2018

2017 Tapia Conference

Runtime Solutions to Apply Non-volatile Memories in Future Computer Systems


Hoda Aghaei Khouzani, University of Delaware


Main memory has been the performance and energy bottleneck of almost all computer systems. For dozens of years, the continuous advances of system design, applications, and technology makes the role of main memory more critical. Moreover, DRAM as the mainstream main memory technology is experiencing many technology scaling challenges that make its capacity, energy-efficiency, and reliability questionable. Fortunately, with the emergence of new memory technologies, a new path to address the limitations of DRAM has appeared. These technologies are non-volatile and have the advantage of higher scalability beyond DRAM with near zero static power consumption. In my PhD thesis, the applicability of two of these technologies, namely Phase Change Memory (PCM) and Domain Wall Memory (DWM) as a replacement for DRAM is explored. Alongside their benefits, PCM suffers from limited write endurance, long write latency, and high write energy, while the main challenge to employ DWM is due to its sequential access structure which requires shift operations to align the data of interest to the access port. Three different solutions are proposed to either hide these shortcomings or use them with respect to the system’s advantage. Specifically, for PCM-based main memory, first a wear-resistant page allocation algorithm is designed by leveraging the existing segment information in OS, so as to prolong PCM lifetime to the maximum extend with almost no extra overhead. Then to hide the write performance and energy limitations of PCM, a hybrid DRAM-PCM main memory is applied, and a conflict miss aware page allocation algorithm is proposed to further improve it. At last, the latency of page table accesses in a DWM-based main memory is reduced using a pre-shift scheme which, based on the state of each entry in page table, pre-aligns the access port to hide read and write latency.